Essentials of Programmable Logic Design
Target Audience
Digital designers new to FPGA design who need to learn the FPGA design cycle, or those who have a working knowledge of HDL (VHDL or Verilog) and seek to learn the major aspects of the Vivado Design Suite
Description
This workshop provides introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those unfamiliar with the
Vivado Design Suite Flow.
The focus is on:
- Introduction to Xilinx FPGA Architecture and 3D ICs
- How to build an effective FPGA design using the Vivado Design Suite Tools
- Explanation of the Vivado Design Suite project and non-project flows
- Basic design analysis
- Using Tcl commands
- Managing IP
Advanced Programmable Logic Design
Target Audience
Digital designers who want to increase their exposure of the Vivado FPGA design Suite, or those who have a working knowledge of HDL (VHDL or Verilog) and seek to increase their productivity using more of the major aspects of the Vivado Design Suite
Description
This workshop provides an deeper examination of the Vivado® Design Suite and demonstrates the FPGA design flow for those wanting to go beyond the basics and learn more advanced Vivado Design Suite flows
The emphasis is on:
- Simulation, synthesis, and implementation of a design
- Advanced FPGA configuration, such as daisy chain and gang, for configuring multiple FPGAs in a system
- Xilinx security features, bitstream encryption, and authentication using AES for design and IP security
- Synchronous design techniques
- Xilinx FPGA power estimation tools throughout the design cycle
- Floorplanning techniques to improve design performance
- Advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Advanced XDC and Timing Analysis
Target Audience
Designers who wish to better understand how apply XDC constraints and perform static timing analysis on an design in the Vivado Design Suite.
Description
This workshop provides an exploration of the underlying database and static timing analysis (STA) mechanisms in the Vivado Design Suite.
The focus is on:
- Utilizing Tcl commands to efficiently navigate the design
- Understanding and creating Xilinx design constraints (XDC)
- Learning appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces
- Understanding of timing constraint priority
- Generating and reading timing reports
- FPGA design best practices to improve design speed and reliability
- Learning optimum system reset design
- Understanding synchronization circuits
- Learning optimum HDL coding techniques
- Timing closure techniques
Advanced Design Techniques
Target Audience
Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional, timing, and power closure
Description
This workshop provides an examination of how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results.
The emphasis is on:
- Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
- Using recommended coding techniques
- Creating a test bench and running simulation for functional verification
- Applying initial design checks and reviewing timing summary and methodology reports for a design
- Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
- Performing quality of results (QoR) assessments at different stages to improve the QoR score
- Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
- Reviewing the importance of power closure and device selection
- Estimating power consumption by using the Vivado® Design Suite Power Report utility and performing power optimization on a design
- Identifying Versal® ACAP power and thermal solutions
- Utilizing architecture features to improve a design’s power consumption
Advanced Timing Closure
Target Audience
Software and hardware developers, system architects, and anyone who wants to learn about advanced timing closure techniques
Description
This workshop provides a detailed exploration of how to apply advanced timing closure techniques and to achieve timing closure for a given design.
The emphasis is on:
- Applying initial design checks and reviewing timing summary and methodology reports for a design
- Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
- Identifying and resolving setup and hold violations
- Learning techniques to improve design speed and reliability
- Reducing logic delays, net delays, and congestion in a design
- Improving clock skew and clock uncertainty
- Optimum HDL coding techniques
- Understanding synthesis options
- Advanced timing closure techniques
- Performing Pblock-based and super logic region (SLR)-based analysis to identify challenges and improve timing closure
- Performing quality of results (QoR) assessments at different stages to improve the QoR score
- Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
UltraFast Design Methodology
Target Audience
Engineers who wish to learn FPGA design best practices to increase design performance and development productivity
Description
This workshop provides users with the techniques and knowledge to improve design speed and reliability by using the UltraFast™ Design Methodology and the Vivado® Design Suite.
The focus is on:
- Optimizing system reset design and synchronization circuits
- Employing best practice HDL coding techniques
- Applying appropriate timing closure techniques
- Reviewing an UltraFast Design Methodology case study
Debugging AMD-Xilinx Hardware Designs
Target Audience
System and logic designers who want to minimize verification and debug time
Description
As FPGA designs become increasingly more complex, designers continue to look for ways to reduce design and debug time. The powerful, yet easy-to-use, Vivado logic analyzer debug solution helps minimize the amount of time required for verification and debug. This workshop provides an examination of how to use debug tools in the Vivado® Design Suite to address advanced verification/debugging challenges.
The emphasis is on:
- Introducing the cores and tools available for debugging programmable logic
- Illustrating how to use the triggers effectively
- Effective debug techniques and methodologies to reduce overall design development time
- Benefits of debug using in-system IBERT
- Serial transceiver built-in test features to validate a serial link
Dynamic Function Exchange (Partial Reconfiguration)
Target Audience
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need to understand Dynamic Function eXchange techniques
Description
This workshop provides a detailed look at how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.
The emphasis is on:
- Identifying best design practices and understanding the subtleties of the DFX design flow
- Using the DFX Controller and DFX Decoupler IP in the DFX process
- Implementing DFX in an embedded system environment
- Applying appropriate debugging techniques on DFX designs
- Employing best practice coding styles for a DFX system
Designing with Xilinx Serial Transceivers
Target Audience
FPGA designers and logic designers interested in using high speed serial transceivers in AMD-Xilinx devices
Description
This workshop provides users with the knowledge of how to employ serial transceivers in UltraScale™ and UltraScale+™ FPGA designs or Zynq® UltraScale+ MPSoC designs.
The focus is on:
- Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection
- Utilizing the Transceivers Wizards to instantiate transceiver primitives
- Synthesizing and implementing transceiver designs
- Taking into account board design as it relates to the transceivers
- Testing and debugging